1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
Japanese Laid Open Patent Application JP, 2004-23093A discloses a trench type flash memory. This flash memory includes: a substrate having a trench; a gate structure; a source region placed in the substrate around the bottom of the trench; and a drain region placed in the substrate around the top of the trench. A tunnel oxide layer, a floating gate, a gate dielectric layer and a control gate are placed in the gate structure, in the order starting from the outer side to the inner side in the trench. Also, the control gate is surrounded and coated by the tunnel oxide layer, the floating gate and the gate dielectric layer.
Also, a split gate type flash memory is known. According to this split gate type flash memory, not only a control gate but also an assistant gate (selection gate) needs to be turned on, in order to turn on a transistor. Thus, even if charges are excessively removed from the floating gate, an excessive removal problem in which a channel region is always conductive is prevented. Also, with a source side injection (SSI), the injection efficiency of hot electrons is improved as compared with a case of a stack gate type flash memory.
Also, Japanese Laid Open Patent Application JP, 2002-373948A discloses a trench split gate type flash memory. FIG. 1 is a sectional view showing a structure of this conventional trench split gate type flash memory cell. This flash memory cell includes a P-type substrate 100, a deep N-well layer 102 and a P-well layer 104. The region doped at a high concentration inside the deep N-well layer forms a source region 106. An assistant gate region 108 on the source region 106 includes a polysilicon layer (assistant gate) 110 and an oxide layer 112. A gate 114 is located on the P-well layer 104 on one side of the assistant gate region 108. The gate 114 has a first polysilicon layer 116, a second polysilicon layer 118 and an insulating layer 120. A drain layer 107 is embedded in the P-well layer 104 on one side of the gate 114. Metal silicon compound layers 122 are formed on the surfaces of the drain region 107 and the polysilicon layer 110.
According to the technique disclosed in JP, 2002-373948A, the floating gate (first polysilicon layer 116) is formed by using a mask pattern. Thus, the size of the floating gate is the minimum manufacturing dimension (feature size) F or more. In this case, the minimum value of the size in a channel direction of a memory cell is “2×F”, and the minimum value of the area of the memory cell is “(2×F)2=4×F2” in principle.
Recently, the capacity of a flash memory has been increased more and more. Thus, the further reduction in a memory cell size, the further improvement of an integration degree and the further drop in a bit cost are desired.